The present invention relates to a method of fabricating a semiconductor device, and more particularly relates to a method of fabricating a semiconductor device which can minimize damage to an oxide layer when a nitride layer formed on the oxide layer is etched.
In semiconductor devices, a non-volatile memory device may include a charge storage layer formed of an insulating layer (for example, a nitride layer) instead of a polysilicon layer which is a conductive layer.
The non-volatile memory device in which the charge storage layer is formed of a conductive layer has a disadvantage that if there is a fine defect on a floating gate, a retention time of charges becomes significantly lowered. However, in the non-volatile memory device in which an insulating layer such as a nitride layer is formed as the charge storage layer, there is an advantage that process defects are relatively reduced due to a property of the nitride layer.
In addition, in the non-volatile memory device in which the charge storage layer is formed of a conductive layer, since a tunnel insulating layer having a thickness of approximately 70 Å or more is formed below a floating gate, there is a limit in realizing a low voltage operation and a high speed operation of the semiconductor device. In the non-volatile memory device in which an insulating layer acts as the charge storage layer, however, it is possible to make a thickness of a direct tunneling insulating layer formed below the charge storage layer become smaller. Thus, the memory device may operate at a low voltage and low power with a high speed.
In general, when the non-volatile memory device in which an insulating layer is utilized as the charge storage layer, an isolation layer is formed on a semiconductor substrate by a shallow trench isolation (STI) process, and an oxide layer as the direct tunneling insulating layer, a nitride layer as the charge storage layer for storing electric charge therein, an oxide layer as the charge blocking layer and a conductive layer as a gate electrode layer are then formed on the semiconductor substrate including the isolation layer. Subsequently, an etching process for forming a gate pattern is performed to form a gate constituting the memory cell.
As described above, however, since the direct tunneling insulating layer has an extremely small thickness, if the exposed direct tunneling insulating layer is etched together with the charge storage layer during an etching process for the charge storage layer, an active region of the semiconductor substrate is directly exposed so that the active region may be damaged. As a result, an operational characteristic of the non-volatile memory device may be adversely affected.
In the process for fabricating the semiconductor device, after forming a gate on a gate insulating layer, a gate spacer can be formed on a side wall of the gate for protecting the gate. In general, an insulating layer, for example, a nitride layer having a thickness sufficient for maintaining a step of the gate, is formed on the semiconductor substrate including the gate. An anisotropic etching process for the nitride layer is then performed to form the gate spacer. However, during the etching process for the nitride layer, the exposed gate insulating layer can be etched together with the nitride layer. In this case, the active region of the semiconductor substrate is also directly exposed so that the active region may be damaged. Due to a damage of the active region, a characteristic of the non-volatile memory device can be lowered.